Programming FPGA and CRIO

In this article, I wanted to briefly go through few practices that I use to develop a compact rio application. A full Compact RIO controller combines FPGA with real time processor. Labview developer could utilise all target levels to develop machine app that would offer maximum resources utilization and reliability to mention only few of the benefits. Target levels in this case would be FPGA Programming, CRIO programming and Windows level programming. You can access large amount of analogue data at FPGA level and DMA transfer to CRIO vi. Within CRIO vi, you can perform filtering/conditioning and then use NI Network Stream for transfer data to PC hard drive for permanent storage or to windows vi for display to users.

FPGA programming

At FPGA level, I would acquire all I/O on machine. I would also put all critical machine safety logic in FPGA. 

For instance, if I need to monitor gates and sensors values to determine if it is safe to start machine, I will always utilize FPGA. FPGA is not only reconfigurable software-based hardware but also a controller that is running without operating system and processor. Therefore, FPGA is amongst the most reliable, deterministic controller available for control and measurement application. Programming at FPGA level is also easier and does not involve one to really master architecting application.

‘FPGA programming is so simple that it is like picking inputs, putting function blocks to connect input and ‘creating‘ new outputs, which are as good as hard-wired outputs, Khurram Waris said’.

At FPGA levels, you could simply put code in while loop running unconditionally with False constant wired to termination input. You can create as many while loop as you wish running unconditionally and continuously as long as FPGA resources are available and you can build an executable vi. Below I have just shown how you could create simple while loop for acquisition and signal generation.

To transfer data i.e Analogue data for high bandwidth throughput into another target for instance real time controller of CRIO PAC, you can use DMA FIFO transfer. Below, I have acquired Aanlogue inputs and used local variable instance in another loop to transfer all analogue inputs to real time controller for further processing.

Once you have completely built FPGA vi, you could then set FPGA vi to run as soon as loaded using properties menu. This would ensure that any safety logic that you have implemented in your design code would be protecting machine and environment as soon as power is established to the machine. This is vital for safety-critical application and would also enhance Safety Integrity Level SIL of the machine.

RT CRIO Level Programming

You can design RT vi like any other vi. The benefits of programming at RT level include determinism of real time controller especially when it runs real time operating system. You can also use timed loops and assign tasks based on priority and threads executions. Hence we have another controller to execute multi-threaded programming.

I would suggest using Network Streams and deploy on RT target to stream data continuously from RT level to Windows level.

Windows Level VI

Windows level vi would include operator interface that user would use to run the machine or test measurement system. It would display all analogue readouts and diagnostics data to the operator. You can also use Network Stream instance that you created at RT level to read all data streamed to the PC and store it in PC hardware for later analysis.

In this article, I wanted to briefly visit labview programming at three target levels when using compact rio PAC controller. For further information, please feel free to get in touch using the details on this website..